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1M x 64-Bit Dynamic RAM Module
HYM 641010GS-60/-70 HYM 641020GS-60/-70
Advanced Information
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1 048 576 words by 64-bit organization Fast access and cycle time 60 ns access time 110 ns cycle time (-60 version) 70 ns access time 130 ns cycle time (-70 version) Fast page mode capability with 40 ns cycle time (-60 version) 45 ns cycle time (-70 version) Single + 5 V ( 10 %) supply Low power dissipation max. 9680 mW active (-60 version) max. 8800 mW active (-70 version) CMOS - 451 mW standby TTL - 550 mW standby
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CAS-before-RAS refresh, RAS-only-refresh Byte Write Capability 16 decoupling capacitors mounted on substrate All inputs, outputs and clock fully TTL compatible 4 Byte interleave enabled, Dual Address inputs (A0/B0) Buffered inputs except RAS and DQ 168 pin, dual read-out, Single in-Line Memory Module Utilizes sixteen 1M x 4 -DRAMs (HYB 514400BJ/BT) and four BiCMOS 8-bit buffers/line drivers 74ABT244 Two version : HYM 641010GS with SOJ-components (8.89 mm module thickness) HYM 641020GS with TSOPII-components (4.06 mm module thickness) 1024 refresh cycles / 16 ms Optimized for use in byte-write non-parity applications Gold contact pads,double sided module with 25.35 mm (1000 mil) height
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Semiconductor Group
1
12.95
HYM 641010/20GS-60/-70 1M x 64 Module
The HYM 641010/20GS-60/-70 is a 8 MByte DRAM module organized as 1 048 576 words by 64bit in a 168-pin, dual read-out, single-in-line package comprising sixteen HYB 514400BJ/BT 1M x 4 DRAMs in 300 mil wide SOJ or TSOPII - packages mounted together with sixteen 0.2 F ceramic decoupling capacitors on a PC board. All inputs except RAS and DQ are buffered by using four BiCMOS 8-bit buffers/line drivers. Each HYB 514400BJ/BT is described in the data sheet and is fully electrically tested and processed according to Siemens standard quality procedure prior to module assembly. After assembly onto the board, a further set of electrical tests is performed. The density and speed of the module can be detected by the use of presence detect pins. Ordering Information Type HYM 641020GS-60 HYM 641020GS-70 HYM 641010GS-60 HYM 641010GS-70 Pin Names A0-A9,B0 DQ0 - DQ63 RAS0, RAS2 CAS0 - CAS7 WE0, WE2 OE0, OE2 Vcc Vss PD1 - PD8 PDE ID0 , ID1 N.C. Presence-Detect and ID-pin Truth Table: Module HYM 641010/20GS-60 HYM 641010/20GS-70 ID0 Vss Vss ID1 Vss Vss PD1 0 0 PD2 0 0 PD3 1 1 PD4 0 0 PD5 0 0 PD6 1 0 PD7 1 1 PD8 1 1 Address Input Data Input/Output Row Address Strobe Column Address Strobe Read / Write Input Output Enable Power (+5 Volt) Ground Presence Detect Pins Presence Detect Enable ID indentification bit No Connection Ordering Code Q67100 - Q2003 on request Q67100 - Q2002 on request Package L-DIM-168-1 L-DIM-168-1 L-DIM-168-1 L-DIM-168-1 Descriptions 60 ns DRAM module 70 ns DRAM module 60 ns DRAM module 70 ns DRAM module
Note: 1 = high level ( driver output), 0 = low level ( driver output) for PDE active ( ground) . For PDE at a high level all PD terminals are in tri-state.
Semiconductor Group
2
HYM 641010/20GS-60/-70 1M x 64 Module
Pin Configuration
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Symbol VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC VSS DQ8 DQ9 DQ10 DQ11 DQ12 VCC DQ13 DQ14 DQ15 NC VSS NC NC VCC WE0 CAS0 CAS2 RAS0 OE0 VSS A0 A2 A4 A6 A8 NC NC VCC NC NC PIN # 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Symbol VSS OE2 RAS2 CAS4 CAS6 WE2 VCC NC NC DQ16 DQ17 VSS DQ18 DQ19 DQ20 DQ21 VCC DQ22 NC NC NC NC DQ23 NC DQ24 VSS DQ25 DQ26 DQ27 DQ28 VCC DQ29 DQ30 DQ31 NC VSS PD1 PD3 PD5 PD7 ID0 VCC PIN # 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Symbol VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 NC VSS DQ40 DQ41 DQ42 DQ43 DQ44 VCC DQ45 DQ46 DQ47 NC VSS NC NC VCC NC CAS1 CAS3 NC NC VSS A1 A3 A5 A7 A9 NC NC VCC NC B0 PIN # 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Symbol VSS NC NC CAS5 CAS7 PDE VCC NC NC DQ48 DQ49 VSS DQ50 DQ51 DQ52 DQ53 VCC DQ54 NC NC NC NC DQ55 NC DQ55 VSS DQ57 DQ58 DQ59 DQ60 VCC DQ61 DQ62 DQ63 NC VSS PD2 PD4 PD6 PD8 ID1 VCC
Semiconductor Group
3
HYM 641010/20GS-60/-70 1M x 64 Module
RAS0 WE0 OE0 CAS0
RAS2 WE2 OE2 CAS4
DQ0-DQ3
I/O1-I/O4 D0
DQ32-DQ35
I/O1-I/O4 D8
DQ4-DQ7 CAS1 DQ8-DQ11
I/O1-I/O4 D1
DQ36-DQ39
I/O1-I/O4 D9
CAS5 I/O1-I/O4 D2 DQ40-DQ43 I/O1-I/O4 D10
DQ12-DQ15
I/O1-I/O4 D3
DQ44-DQ47
I/O1-I/O4 D11
CAS2 DQ16-DQ19 I/O1-I/O4 D4
CAS6 DQ48-DQ51 I/O1-I/O4 D12
DQ20-DQ23
I/O1-I/O4 D5
DQ52-DQ55
I/O1-I/O4 D13
CAS3 DQ24-DQ27 I/O1-I/O4 D6
CAS7 DQ56-DQ59 I/O1-I/O4 D14
DQ28-DQ31
I/O1-I/O4 D7
DQ60-DQ63
I/O1-I/O4 D15
A0 B0 A1-A9
D0 - D7 D8 - D15 D0 - D17 Vcc Vss D0-D15, buffers
Block Diagram
Semiconductor Group
4
HYM 641010/20GS-60/-70 1M x 64 Module
Absolute Maximum Ratings Operating temperature range ......................................................................................... 0 to + 70 C Storage temperature range...................................................................................... - 55 to + 125 C Input/output voltage ........................................................................................................ - 1 to + 7 V Power supply voltage...................................................................................................... - 1 to + 7 V Power dissipation................................................................................................................ 12,32 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics 1) TA = 0 to 70 C; VCC = 5 V 10 % Parameter Symbol Limit Values min. Input high voltage Input low voltage Output high voltage (IOUT = - 5 mA) Output low voltage (IOUT = 4.2 mA) Input leakage current (0 V < VIN < 6.5 V, all other pins = 0 V) Output leakage current (DO is disabled, 0 V < VOUT < 5.5 V) max. 5.5 0.8 - 0.4 10 10 V V V V A A Unit Test Condition - - - - - -
VIH VIL VOH VOL II(L) IO(L)
2.4 - 1.0 2.4 - - 10 - 10
Average VCC supply current: ICC1 HYM 641010/20GS-60 HYM 641010/20GS-70 (RAS, CAS, address cycling, tRC = tRC min.) Standby VCC supply current (RAS = CAS = VIH)
- -
1760 1600
mA mA
2), 3)
ICC2
-
50
mA
-
Average VCC supply current during RAS ICC3 only refresh cycles: HYM 641010/20GS-60 HYM 641010/20GS-70 (RAS cycling, CAS = VIH , tRC = tRC min.)
2)
- -
1760 1600
mA mA
Semiconductor Group
5
HYM 641010/20GS-60/-70 1M x 64 Module
DC Characteristics (cont'd) Parameter
1)
Symbol
Limit Values min. max.
Unit
Test Condition
2), 3)
ICC4 Average VCC supply current during fast page mode: HYM 641010/20GS-60 HYM 641010/20GS-70
(RAS = VIL, CAS, address cycling tPC = tPC min.) Standby VCC supply current (RAS = CAS = VCC - 0.2 V)
- -
1120 1120
mA mA
ICC5
-
30
mA
-
Average VCC supply current during ICC6 CAS-before-RAS refresh mode: HYM 641010/20GS-60 HYM 641010/20GS-70 (RAS, CAS cycling, tRC = tRC min.)
1)
- -
1760 1600
mA mA
Capacitance TA = 0 to 70 C; VCC = 5 V 10 %; f = 1 MHz Parameter Input capacitance (A0 to A9,B0) Input capacitance (RAS0, RAS2) Input capacitance (CAS0-CAS7) Input capacitance (WE0,WE2,OE0,OE2) I/O capacitance (DQ0-DQ63) Symbol min. Limit Values max. 10 50 15 15 15 pF pF pF pF pF - - - - - Unit
CI1 CI2 CI3 CI4 CIO1
Semiconductor Group
6
HYM 641010/20GS-60/-70 1M x 64 Module
AC Characteristics (note: 5,6,7,8) TA = 0 to 70 C,VCC = 5.0 10 % Parameter Symbol min. -60 max. min. -70 max. Unit Note
common parameters
Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width CAS precharge time Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period tRC tRP tRAS tCAS tCP tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH 110 40 60 15 10 5 8 2 15 18 13 20 58 10 3 - - - 100k 100k - - - - - 40 25 - - - 30 16 130 50 70 20 10 5 8 2 20 18 13 25 68 10 3 - - - 100k 100k - - - - - 45 30 - - - 30 16 ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns
9 10 11 9 12
12
9 10 9 7
tCRP
tT tREF
Read Cycle
Access time from RAS Access time from CAS Access time from column address OE access time Column address to RAS lead time Read command setup time Read command hold time Read command hold time referenced to RAS CAS to output in low-Z Output buffer turn-off delay Output buffer turn-off delay from OE tRAC tCAC tAA tOEA tRAL tRCS tRCH tRRH tCLZ tOFF tOEZ - - - - 35 2 2 0 2 - - 60 20 35 20 - - - - - 20 20 - - - - 40 2 2 0 2 - - 70 25 40 25 - - - - - 25 25 ns ns ns ns ns ns ns ns ns ns ns
13,14
9,13,14 9,13, 15
9,13 9 11 11,16 16 11,13 9,17 9,17
Semiconductor Group
7
HYM 641010/20GS-60/-70 1M x 64 Module
AC Characteristics (cont'd)(note: 5,6,7,8) TA = 0 to 70 C,VCC = 5.0 10 % Parameter Symbol min. CAS delay time from Din Data to OE low delay CAS high to data delay OE high to data delay tDZC tDZO tCDD tODD 0 0 20 20 -60 max. - - - - min. 0 0 25 25 -70 max. - - - - ns ns ns ns
18 18 9,19 9,19
Unit
Note
Write Cycle
Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time tWCH tWP tWCS tRWL tCWL tDS tDH 15 10 2 20 15 -2 15 - - - - - - - 15 10 2 25 20 -2 20 - - - - - - - ns ns ns ns ns ns ns
10,21 9,21 11,20 9 9
Read-Modify-Write Cycle
Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE command hold time tRWC tRWD tCWD tAWD tOEH 155 82 37 52 13 - - - - - 185 97 47 62 18 - - - - - ns ns ns ns ns
9 11,21 11,21 11,21
10
Fast Page Mode Cycle
Fast page mode cycle time Access time from CAS precharge RAS pulse width CAS precharge to RAS Delay tPC tCPA tRAS tRHCP 40 - 60 40 - 40 200k - 45 - 70 45 - 45 200k - ns ns ns ns
9 9,13
Semiconductor Group
8
HYM 641010/20GS-60/-70 1M x 64 Module
AC Characteristics (cont'd)(note: 5,6,7,8) TA = 0 to 70 C,VCC = 5.0 10 % Parameter Symbol min. -60 max. min. -70 max. Unit Note
Fast Page Mode Read-Modify-Write Cycle
Fast page mode read-write cycle time CAS precharge to WE tPRWC tCPWD 82 57 - - 97 67 - - ns ns
11 11,21
CAS-before-RAS Refresh Cycle
CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write hold time referenced to RAS tCSR tCHR tRPC tWRP tWRH 12 8 5 12 8 - - - - - 12 8 5 12 8 - - - - - ns ns ns ns ns 11 10
11
10
Presence Detect Read Cycle
PDE to valid presence detect data PDE inactive to presence detects inactive tPD tPDOFF - 0 10 10 ns ns
Semiconductor Group
9
HYM 641010/20GS-60/-70 1M x 64 Module
Notes:
All voltages are referenced to VSS. ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate. ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. Address can be changed once or less while RAS = Vil.In the case of ICC4 it can be changed once or less during a fast page mode cycle ( tpc). 5) An initial pause of 100 s is required after power-up followed by 8 RAS-only-refresh cycles, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 5 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 8) The specified timings include buffer, loading and skew delay adders: 2ns minimum, 5ns (CAS, WE, OE, addresses) maximum delay, no pulse shrinkage to the DRAM device timings. The data and RAS signals are not buffered, which preserves the DRAMs access specification of 50ns and 60ns. 9) A +5ns timing skew from the DRAM to the module resulted from the addition of line drivers. 10) A -2ns timing skew from the DRAM to the module resulted from the addition of line drivers. 11) A +2ns timing skew from the DRAM to the module resulted from the addition of line drivers. 12) A -2ns (min.) and a -5ns (max.) timing skew from the DRAM to the module resulted from the addition of line drivers. 13) Measured with the specified current load and 100 pF at Voh = 2.4 V and Vol = 0.4 V. 14) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 15) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 16) Either tRCH or tRRH must be satisfied for a read cycle. 17) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 18) Either tDZC or tDZO must be satisfied. 19) Either tCDD or tODD must be satisfied. 20) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 21) These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in ReadModify-Write cycles. 1) 2) 3) 4)
Semiconductor Group
10
HYM 641010/20GS-60/-70 1M x 64 Module
L-DIM-168-1 Module package (dual read-out, single in-line memory module)
GLD05860
Semiconductor Group
11

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